Share variables between verilog file and niosII application file(.c file)

In your component HDL definition you declared a 4-bit addess range:

...
// slave interface
input  slave_address;
...

That means you can't access data a offset 20.

Slave maps into Nios memory from ONCHIP_MEMORY2_BASE to ONCHIP_MEMORY2_BASE+15. You should see this slave address range in Qsys, too.

Anyway the correct syntax is

variable = IORD(ONCHIP_MEMORY2_BASE, 20);

Please also note that Nios use byte addressing, so you possibly need to discard the 2 LSB of address when accessing 32bit data.

I can't understand the linker error about .bss section: I'm concerned it is related to the IORD call.

I'd rather think you made sort of mess with linker settings after you added the new onchip memory device. Do you map any memory section into it? How is 'variable' defined?