Share variables between verilog file and niosII application file(.c file)

Ok... No issues

Anyways i will continue the activity of memory mapped slave with onchip memory and atleast make sure that i can access same onchip memory address locations via HDL and NiosII.

if you can kindly confirm my assumptions of earlier post. and please have a look at my implementations below.

the HDL code is getting compiled, but niosIi code is giving error.

Kindly help..

HDL part

module DE2_115_GOLDEN_TOP(

....

// signals to connect to an Avalon-MM slave interface

slave_address,

slave_read,

slave_write,

slave_readdata,

slave_writedata,

slave_byteenable,

// signals to connect to custom user logic (up to 16 input and output pairs)

user_dataout_0,

user_datain_0,

// optional signals so that your external logic knows what location is being accessed

user_chipselect,

user_byteenable,

user_write,

user_read

);

//=======================================================

// PARAMETER declarations

//=======================================================

parameter DATA_WIDTH = 16; // word size of each input and output register

parameter ENABLE_SYNC_SIGNALS = 0; // only used by the component .tcl file, 1 to expose user_chipselect/write/read, 0 to stub them

parameter MODE_0 = 2; // 0 = Output, 1 = Input, 2 = Ouput and Input, 3 = Output with loopback, 4 = Disabled

----------------------------------------------------------

// slave interface

input [3:0] slave_address;

input slave_read;

input slave_write;

output reg [DATA_WIDTH-1:0] slave_readdata;

input [DATA_WIDTH-1:0] slave_writedata;

input [(DATA_WIDTH/8)-1:0] slave_byteenable;

// user interface

output wire [DATA_WIDTH-1:0] user_dataout_0;

input [DATA_WIDTH-1:0] user_datain_0;

output wire [15:0] user_chipselect;

output wire [(DATA_WIDTH/8)-1:0] user_byteenable;

output wire user_write;

output wire user_read;

*** reg [data_width-1:0] ram[10];

assign user_write = slave_write; // outputs are registed so need a delayed copy of the write signal

assign user_read = slave_read;

// using Qsys i had integrated niosII, PIO lEd, on chip memory and Avalon MM slave

niosII_Qsys inst_niosII_Qsys (

.clk_clk (CLOCK_50), // clk.clk

.redled_external_connection_export (LEDG), // redled_external_connection.export

.amm_slave_ui_dataout_0 (slave_writedata), // amm_slave_ui.dataout_0

.amm_slave_ui_datain_0 (slave_readdata) // .datain_0

);

// finally -----------------------------------------------------------------------------

always @(posedge CLOCK_50)

begin

swreg = SW;

if(swreg[0] == 1)

begin

flag = 1;

regledr[0] = 1;

end

else

begin

flag = 0;

regledr[0] = 0;

end

// write to memory only once when sw is turned ON

if(flag == 1) begin

flag = 2;

// onchip memory address range starts at 0x20000,

// i have directly written data 5 to the first array index. i don't know at which onchip address the ram variable starts.

ram[0] <= 5;

/*if(slave_write)

ram[slave_address] <= slave_writedata;

else if (slave_read)

slave_readdata <= ram[slave_address]; */

end

end

NiosII code

//Auto generated code# define ONCHIP_MEMORY2_BASE 0x20000 // ONCHIP_MEMORY2_BASE starts address

main .c file

variable = IORD((ONCHIP_MEMORY2_BASE+20), 0);

In nios II when i try to read onchip memory address location (ONCHIP_MEMORY2_BASE + 20) using the above statement it gives me memory error

as

"address 0xaddf7c of niosII_SW.elf section `.bss' is not within region `onchip_memory2' ""address 0xaddf7c of niosII_SW.elf section `.onchip_memory2' is not within region `onchip_memory2'"