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The easiest way would be to have a second descriptor chain ready to go so that when the interrupt fires from the completion of the first chain you can quickly write the start of the second chain. Unfortunately this means you will have a little bit of dead time between the chains.
Another way to do this is to start building up the second chain which is linked to the first one but make sure the owned by hardware bit isn't set on the beginning of the second chain. Then it becomes a matter of flipping that bit and starting the SGDMA back up. Again this will lead to some dead time between descriptors. Last but not least you could use a polling approach to figure out where the SGDMA is in the chain. Using this same owned by hardware bit flipping approach if you can create the second descriptor chain and flip that bit fast enough then there will be no dead time between the descriptor chains. That said you have to worry about race conditions since you'll have two masters (CPU and SGDMA) accessing the same memory location.
This trickiness is why I made it possible to fire an interrupt on the completion of any descriptor in my implementation.
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Hm, well it gives me status result of 0x8e, which says that the chain is complete. Is there a method to start the same chain again? I suppose I have two descriptors prepared in my current chain.
I can wait a small period of time since I have to receive a packet and place it to InterNiche packet buffer, which is a small struct with some additional variables.
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