Forum Discussion
Altera_Forum
Honored Contributor
14 years agoAh, yes, I have had to solve that one too ... the following is just typed in (so the VHDL syntax might be slightly wrong):
package simulation_pkg is
function simulation returns boolean;
end package simulation_pkg;
package simulation_pkg body is
function simulation returns boolean is
variable result := false;
begin
-- altera translate_off
result := true;
-- altera translate_on
return result;
end function;
end package simulation_pkg body ;
The other synthesis constraint that can be useful is -- synthesis read_comments_as_HDL on -- synthesis read_comments_as_HDL off Cheers, Dave