Honored ContributorHello,
is it possible to change a value in a VHDL package file from a component TCL script? I have a component which is parameterized by a constant value which is set in a package: package constants_pkg is --! @brief Symbol width of the Avalon bus constant avalon_symbol_width_c : integer:= 8; end package constants_pkg; package body constants_pkg is end package body constants_pkg;
Honored Contributoryou could get the TCL script to modify the VHDL and change the constant.
Honored ContributorHere's some Tcl code I use in an SOPC _hw.tcl file ...
# Replace the generic values (suffixed by _VAL in the template)
set params {
AWIDTH
BWIDTH
DWIDTH
CLK_FREQUENCY
WRITE_CYCLE
READ_CYCLE
AWIDTH_MINUS_1
BWIDTH_MINUS_1
DWIDTH_MINUS_1}
foreach param $params {
eval set buffer \ \$buffer\]
}
u1: ftdi_to_avalon_mm_bridge
generic map (
CLK_FREQUENCY => CLK_FREQUENCY_VAL,
READ_CYCLE => READ_CYCLE_VAL,
WRITE_CYCLE => WRITE_CYCLE_VAL,
AWIDTH => AWIDTH_VAL,
BWIDTH => BWIDTH_VAL,
DWIDTH => DWIDTH_VAL
)
port map (
-- Reset and clock
rstN => rstN,
clk => clk,
-- FTDI interface
ftdi_rxfN => ftdi_rxfN,
ftdi_txeN => ftdi_txeN,
ftdi_rdN => ftdi_rdN,
ftdi_wr => ftdi_wr,
ftdi_dq_oe => ftdi_dq_oe,
ftdi_dq_out => ftdi_dq_out,
ftdi_dq => ftdi_dq,
-- Avalon-MM interface
avm_read => avm_read,
avm_write => avm_write,
avm_byteen => avm_byteen,
avm_addr => avm_addr,
avm_wrdata => avm_wrdata,
avm_rddata => avm_rddata,
avm_wait => avm_wait,
avm_rdvalid => avm_rdvalid
);
Would the script then modify the code? The best solution for me would be that it overrides the value given in the package for the generation of the system but it shouldn't touch the file.
If this is not possible I would be interested in your solution which modifies the constant. Do you have an example on how to do that?Honored ContributorHonored Contributori recently switched from make files and bash scripts to python for project builds
the language is so pleasant and powerful that i've started to do this sort of dynamic generation my strategy is to have golden files which get copied into the generated project directory. the files can be modified upon copyHonored ContributorHonored ContributorHonored ContributorAh, yes, I have had to solve that one too ... the following is just typed in (so the VHDL syntax might be slightly wrong):
package simulation_pkg is
function simulation returns boolean;
end package simulation_pkg;
package simulation_pkg body is
function simulation returns boolean is
variable result := false;
begin
-- altera translate_off
result := true;
-- altera translate_on
return result;
end function;
end package simulation_pkg body ;
-- synthesis read_comments_as_HDL on
-- synthesis read_comments_as_HDL off
