Set properties of VHDL package file from component TCL file

you could get the TCL script to modify the VHDL and change the constant.

Here's some Tcl code I use in an SOPC _hw.tcl file ...

   #  Replace the generic values (suffixed by _VAL in the template)
    set params {
        AWIDTH
        BWIDTH
        DWIDTH
        CLK_FREQUENCY
        WRITE_CYCLE
        READ_CYCLE
        AWIDTH_MINUS_1
        BWIDTH_MINUS_1
        DWIDTH_MINUS_1}
    foreach param $params {    
        eval set buffer \ \$buffer\]
    }

    u1: ftdi_to_avalon_mm_bridge 
        generic map (
            CLK_FREQUENCY => CLK_FREQUENCY_VAL,
            READ_CYCLE    => READ_CYCLE_VAL,
            WRITE_CYCLE   => WRITE_CYCLE_VAL,
            AWIDTH        => AWIDTH_VAL,
            BWIDTH        => BWIDTH_VAL,
            DWIDTH        => DWIDTH_VAL
        )
        port map (
            -- Reset and clock
            rstN        => rstN,
            clk         => clk,
            -- FTDI interface
            ftdi_rxfN   => ftdi_rxfN,
            ftdi_txeN   => ftdi_txeN,
            ftdi_rdN    => ftdi_rdN,
            ftdi_wr     => ftdi_wr,
            ftdi_dq_oe  => ftdi_dq_oe,
            ftdi_dq_out => ftdi_dq_out,
            ftdi_dq     => ftdi_dq,
            -- Avalon-MM interface
            avm_read    => avm_read,
            avm_write   => avm_write,
            avm_byteen  => avm_byteen,
            avm_addr    => avm_addr,
            avm_wrdata  => avm_wrdata,
            avm_rddata  => avm_rddata,
            avm_wait    => avm_wait,
            avm_rdvalid => avm_rdvalid
        );

Would the script then modify the code? The best solution for me would be that it overrides the value given in the package for the generation of the system but it shouldn't touch the file.

i recently switched from make files and bash scripts to python for project builds

Ah, yes, I have had to solve that one too ... the following is just typed in (so the VHDL syntax might be slightly wrong):

package simulation_pkg is
     function simulation returns boolean;
end package simulation_pkg;
package simulation_pkg body is
     function simulation returns boolean is
         variable result := false;
     begin
        -- altera translate_off
        result := true;
        -- altera translate_on
        return result;
     end function;
end package simulation_pkg body ;

-- synthesis read_comments_as_HDL on
-- synthesis read_comments_as_HDL off