set_output_delay explained for dummies

Thank you very much for the explanation and I will read through that guide. I'm closing in on understanding, but I'm still not there.

One thing that confuses me about your post is "Looking at -max 3.0 ... then the FPGA must get the signal out dout[*] ports by time 7ns of it will fail setup".

In my example scenario, the external device is expecting these events at its input pins:

t=0.0, clock edge

t= (0.0,1.0) data does not need to be valid.

t = [1.0, 3.0] data must be valid.

t = (3.0,10.0) data does not need to be valid.

So when you say "get the signal out by 7ns", what does that mean? If the data isn't valid until 7ns, my external device will not work. Am I misinterpreting what you are saying?

Thanks for the plug, gj_leeson. :)

http://www.alterawiki.com/wiki/timequest_user_guide

It's probably better explained in the document, but here goes a condensed version. First, I think of set_output_delay as if it were describing a circuit. So if you have:

create_clock -period 10.0 -name fpga_clk [get_ports fpga_clk]

derive_pll_clocks ;#Let's say fpga_clk drives a PLL but the output is also 10ns

create_clock -period 10.0 -name ext_clk ;# This is a virtual clock, because it's not applied to anything physical inside the design

set_output_delay -max 3.0 -clock ext_clk [get_ports {dout[*]}]

set_output_delay -min -1.0 -clock ext_clk [get_ports {dout[*]}]

The set_output_delay constraint says there is an external register who'd D port is driven by dout[*] and who's CLK port is driven by ext_clk. Before even worrying about the -max/-min values, note that we know have a reg to reg transfer, where the launch register is the output register in the IO cell and is driven by the PLL clock, and the latch register is this one you've just described in your constraint. They are both driven by 10ns clocks, so the default setup relationship is 10ns and the hold is 0ns. We can do timing analysis like any reg to reg path. The -max and -min values state what the external max and min delays are to this external register. Looking at -max 3.0 since it's easier to understand, this says there is a 3ns delay to the external register. Since we have a 10ns setup relationship, then the FPGA must get the signal out dout[*] ports by time 7ns or it will fail setup. You can think of this simple case to be like a Tco requirement of 7ns. (There are cases where Tco isn't very good, but most of them line up nicely).

I think one of the really hard things to grasp is that this is all dependent on the clock rates. So if someone asks me if "set_output_delay -max 3.0..." is a tight constraint, it all depends. If the clock period is 50ns, then yes, it's very easy. If it's 5ns, it's difficult. Also note that the -max value usually lines up with the Tsu requriement of the external device. So if the Tsu were 2.7ns, and the max board trace delay was 0.3ns, then we would do a -max of 3ns.

The -min value works similarly stating that the external delay could be as short as -1ns. Since our hold relationship between the clocks is 0ns, the data must get across the interface in 0ns. So if the external delay is -1ns, then the FPGA must be at least +1ns to meet timing. In this case, the min value usually matches up to the negative of the external devices hold relationship. So, if your external device had a hold relationship of 1.1ns, and the board trace delay could be as fast as 0.1ns, then the external delay is (-1.1 + 0.1) = -1ns.

Hope that helps.