set_output_delay explained for dummies

Thank you very much for the explanation and I will read through that guide. I'm closing in on understanding, but I'm still not there.

One thing that confuses me about your post is "Looking at -max 3.0 ... then the FPGA must get the signal out dout[*] ports by time 7ns of it will fail setup".

In my example scenario, the external device is expecting these events at its input pins:

t=0.0, clock edge

t= (0.0,1.0) data does not need to be valid.

t = [1.0, 3.0] data must be valid.

t = (3.0,10.0) data does not need to be valid.

So when you say "get the signal out by 7ns", what does that mean? If the data isn't valid until 7ns, my external device will not work. Am I misinterpreting what you are saying?