Sequential Logic in Altera

BadOmen,

I think you are thinking about ActiveHDL which does indeed come with a good set of tutorials for VHDL and Verilog. I guess I need to restate my question about the Altera code.

In the architecture of an LED they have the line clk_en <= std_logic&#39;(&#39;1&#39;); and in the process block they have another statement with std_logic_vector&#39;("0000000000000000000000000000000"). I understand what std_logic and std_logic_vector logic types are and I am assuming that is just a typecast since the clk_en is declared as std_logic, but I&#39;m just double checking.

thanks,

jon