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Altera_Forum
Honored Contributor
Honored ContributorSequential Logic in Altera
Hi, How to write a sequential logic in Altera(Verilog)? How to make use of clock & reset (say in a D flipflop)? Could any one give me one example along with C program.
Altera_ForumHonored Contributor
Honored ContributorBadOmen,
I think you are thinking about ActiveHDL which does indeed come with a good set of tutorials for VHDL and Verilog. I guess I need to restate my question about the Altera code. In the architecture of an LED they have the line clk_en <= std_logic'('1'); and in the process block they have another statement with std_logic_vector'("0000000000000000000000000000000"). I understand what std_logic and std_logic_vector logic types are and I am assuming that is just a typecast since the clk_en is declared as std_logic, but I'm just double checking. thanks, jon
