Forum Discussion
Altera_Forum
Honored Contributor
13 years agoI check some documents about SDRAM design again and run a tcl file which is about board trace model. The tcl file named "ArriaIIGX_DDR3_BTModels.tcl" can be found in some reference designs from Altera.
Now, I get half chance to read those 32 data from SDRAM successfully. In failed cases, most the data read from SDRAM are correct. I'm wondering if the timing issue is the root cause of my problem, because I guess the board trace model helps my design to have a better performance in timing. Thanks.