Hi @all, for a redesign i have to check which performance is better: A 32bit SDRAM with the SOPC-Builder SDRAM Controller (Latency Aware SDRAM Controller Version 6.01) or a 16bit DDRAM with the DDR-Controller (DDR-SDRAM Controller Version 3.40) Both Systems will be clocked at 100MHz. The NIOS also. Therefore no extra clocks are generated by the Avalon-Logic. Make it sense to connect 2 Chips to the Nios to get a 32bit-Bus? Which system has the better performance? Thanx for your suggestions... Bye Marco

Some info can be found in followong graph : testresults (http://users.pandora.be/svhb/test%20results%20jpeg%20algorithm.pdf) Some explanations about the graph : CPU 85 PM DDR MTXA130 DM DDR MTXA130 means : CPU 85 : cpu speed 85Mc, PM DDR MTX 130 = program memory DDR Microtronix core 130Mc DM DDR MTXA130 = data memory (stack, ...) DDR Microtronix core 130Mc All CPUs on 52Mc are NIOSII in a cyclone device All others are NIOSII in CycloneII The CPU is generated as standard (s-version), with smalles possible instruction cache, no data cache (we want to test memory access here!). The algorithme is a JPEG encoder, the different steps in the encoding are measured also. No Hardware optimisations! Synchronuous SRAM seems to be best, but more expensive. Hope this helps. Stefaan

Stefaan: Thanks! That&#39;s great information. I found it interesting that: CPU 52 PM SDRAM MTX150 DM SDRAM MTX150 did worse than: CPU 52 PM SDRAM Alt52 DM SDRAM Alt52 -Brian

--- Quote Start --- originally posted by bgrattan@Sep 18 2006, 04:52 PM stefaan: thanks! that&#39;s great information. i found it interesting that: cpu 52 pm sdram mtx150 dm sdram mtx150 did worse[/b] than: CPU 52 PM SDRAM Alt52 DM SDRAM Alt52 -Brian <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18324) --- Quote End --- [/b] --- Quote End --- Yes, that&#39;s funny. But i think the reason is the different clock. CPU with 52Meg and Ram with 150Meg..... there you need Clock-crossings... Maybe Stefaan can do some more Benchmarks with same frequencys.... Unfortunately there is no comparision between the same frequency like CPU100 PM SDRAM Alt100 DM SDRAM Alt100 32bit vs. CPU100 DDRAM Alt100 DM DDR Alt100 16bit Bye Marco

--- Quote Start --- originally posted by svhb@Sep 18 2006, 03:17 PM some info can be found in followong graph : testresults (http://users.pandora.be/svhb/test%20results%20jpeg%20algorithm.pdf) some explanations about the graph : cpu 85 pm ddr mtxa130 dm ddr mtxa130 means : cpu 85 : cpu speed 85mc, pm ddr mtx 130 = program memory ddr microtronix core 130mc dm ddr mtxa130 = data memory (stack, ...) ddr microtronix core 130mc all cpus on 52mc are niosii in a cyclone device all others are niosii in cycloneii the cpu is generated as standard (s-version), with smalles possible instruction cache, no data cache (we want to test memory access here!). the algorithme is a jpeg encoder, the different steps in the encoding are measured also. no hardware optimisations! synchronuous sram seems to be best, but more expensive. hope this helps. stefaan <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18322) --- quote end --- --- Quote End --- @Stefaan What DDR-Interface was that? 16bit? What SDR-Interface? Also 16bit or 32bit? Can you tell me more details about the hardware? Thanx Marco

If you want to gain decent performance when crossing clock domains, you ought to consider the Avalon to Avalon Bridges project (http://http://www.niosforum.com/pages/project_details.php?p_id=85&t_id=18). Use the asynchronous FIFOed option. Cheers, - slacker

SDRAM vs. DDRAM Performance | Altera Community

13 Replies

Altera_Forum
Honored Contributor
19 years ago
That is interesting.

If DDR 16Bit has a higher performance than SDRam 32Bit then i would like to know if anybody can tell me what the price is about comparing DDR and SDRam to have at the end the same memory size.

Also has anybody any recomendations about the DDR design ?
Where the pittfals are ? PCB, clock-phase, ....

Maybe i should give DDR a try next time ...

Regards.

Michael
Altera_Forum
Honored Contributor
19 years ago
--- Quote Start ---
originally posted by mschmitt@Sep 21 2006, 04:36 PM
that is interesting.

if ddr 16bit has a higher performance than sdram 32bit then i would like to know if anybody can tell me what the price is about comparing ddr and sdram to have at the end the same memory size.

also has anybody any recomendations about the ddr design ?
where the pittfals are ? pcb, clock-phase, ....

maybe i should give ddr a try next time ...

regards.

michael
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18389)
--- quote end ---

--- Quote End ---

The easiest way is to use tje altera core that comes with the dev-board. I think you need a quartus subscription for that??
Altera_Forum
Honored Contributor
19 years ago
Hi Stefaan,

i already have 3 full subscription and already looked into the ip toolchain for DDR but i would like to know what kind of traps there are and where to have a special look after during the implementation of DDR.

Michael

Forum Discussion

SDRAM vs. DDRAM Performance

13 Replies

Recent Discussions

Run-time errors using EMIF in Agilex 5 NIOS-V design

Ashling RISC Free IDE fails to download ELF file

Dual Port Nios V BSP error

set_output_delay explained for dummies

[Test only]How to verify Agilex 3 in radiation tolerant environment