SDRAM timing Violation

Hello.

I am using mt48lc2m32b2 as the SDRAM. My input clock frequency is 80 MHz.

My design is composed of CPU, on-chip mem, SDRAM, JTAG and PLL. The whole system is running on 80 MHz output clock from PLL and the clock to SDRAM is also from PLL, i.e. 80 MHz.

I am getting setup and hold violations as seen in the time quest timing analyzer.

I have not given any clock constraints so far as i don't know how to give.

Can you tell me what could probably be the reason of violation as altera provides direct support of the above mentioned SDRAM in SOPC.

Regards.