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Altera_Forum
Honored Contributor
Honored ContributorSDRAM signals managing
Hi, I'm using qsys to implement a system on Quartus II. I use a DE0-NANO board and I want to access the SDRAM. I want to access it from a Nios II (and also from the hardware design but it's anot...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The hardware that needs to access the SDRAM needs to be written as an Avalon-MM master, so that it can initiate SDRAM reads or writes. --- Quote End --- How do I write it like that? --- Quote Start --- Alternatively, your hardware can be an Avalon-MM slave or Avalon-ST sink/source, and you can use a DMA controller to move data from your component to/from SDRAM. --- Quote End --- I don't need a DMA. --- Quote Start --- That is not a Qsys task. That is the job of the linker script. --- Quote End --- How do I configure the linker? --- Quote Start --- You already have a working SDRAM controller (using the standard Altera Avalon-MM SDRAM controller), why are you trying to use this design? --- Quote End --- That was only for test. Forget it.
