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The hardware that needs to access the SDRAM needs to be written as an Avalon-MM master, so that it can initiate SDRAM reads or writes.
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How do I write it like that?
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Alternatively, your hardware can be an Avalon-MM slave or Avalon-ST sink/source, and you can use a DMA controller to move data from your component to/from SDRAM.
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I don't need a DMA.
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That is not a Qsys task. That is the job of the linker script.
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How do I configure the linker?
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You already have a working SDRAM controller (using the standard Altera Avalon-MM SDRAM controller), why are you trying to use this design?
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That was only for test. Forget it.
Honored Contributor
