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Altera_Forum's avatar
Altera_Forum
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19 years ago

SDRAM problem

Hi,

I have got a Cyclone dev kit (EP1C20) and i'm trying to get a design working that uses SDRAM to store some data. If I write the data and read it back it is valid but if there is a delay between the write and read then the data is no longer valid (has reset). It is as though the SDRAM isn't refreshing correctly (although it's the first time I have used SDRAM so it could be anything as far as I know!) and after a short time the data is lost.

I am using a NIOS II CPU and the MT48LC4M32B2 SDRAM chip that is on the dev kit. The controller is the SDRAM controller in SOPC builder and uses the presets for the MT.. chip.

I think I have the pins connected up according to the Nios Development Board Refernce Manual.

Is there anything else that I should be doing? I am a bit of a novice!

Thanks to anybody that is able to help!!

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Hello GaryJS,

    The described behaviour is typical for a low refresh rate. If you are using a ready reference design which comes with Nios II the system should be ok. Did you test the software with one of these reference designs?

    Regards,

    niosIIuser
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    GaryJS,

    perhaps the clock you specified in SOPC builder is not the clock you've connected to. This could result in a wrong refresh rate.

    Mike
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    I had the same problems with a EP1C20 and this Micron SDram which is obsolete by now and the last time buy will be within the next few weeks.

    So first check that the sdram settings within sopc are as they should be. compare the micron pdf ! check the clock settings. is the sopc entered clock the clock you have ?

    One very important thing is that you must use the dedicated pll outputs for sdram clock and set the pll sdram clock phase as calculated. Check this with a scope !

    we had problems with the signal integrity so consider to set the current on the sdram signals with the assignment editor.

    and finaly use fast input / output / enables

    If you have all the above you will have fun with sdram.

    Regards

    Michael Schmitt
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Thanks for the advice guys. MSchmitt hit it on the head. I had the PLL connected up incorrectly.

    Thanks for the link on the compatability issues! We were planning on using an ISSI device so I will take a read.

    Thanks again!