I&#39;m planning a NiosII design and we need a pile of RAM but don&#39;t need the high bandwidth of SRAM. It&#39;s hard to find SDRAM chips in stock, given their commodity nature, and so I was looking at using an SO-DIMM site instead of a particular SDRAM chip. (That also deals with the problem of someone later deciding we don&#39;t have enough memory.) Hardware-wise, an SO-DIMM looks great (about 3 by 1.5 inches of board space, $30-40 for 128MB 64-bit wide PC133, and $7 or less for the socket). What I&#39;m wondering about is the SDRAM interface SOPC component; can it deal with a memory module? I&#39;m guessing I&#39;ll have to hook up an I2C interface to the SPD port and have the bootloader compare the timing info to the parameters the SDRAM interface was built with. It would be nice if we could add a slave port to the SDRAM interface component and make the timing parameters BIOS-settable, but it&#39;s not a requirement. So, any thoughts, anyone?

Hello Mike, Of course you can use SO-DIMM modules for your design but it is not possible to change the timing behaviour during run-time with the SDRAM controller of the Nios II. Perhaps there are other vendors which provides SDRAM controller to do such things. One solution is to set worst-case timings in SOPC builder and use these for all modules. Or you do the settings for a specific module and sell the board only with theses modules. Using SO-DIMM modules is a good idea but it is also possible that you won’t get these modules after some years because all new notebooks are using DDR or the price is very high (like with the normal SDRAM modules now). But that is only my opinion. Perhaps some others have more detailed information. Bye, niosIIuser

I think you&#39;ll be able to get SDRAM SO-DIMM&#39;s for a very long time. Common sense says they would be available much longer than any single chip you&#39;d pick. Our board that&#39;s been shipping for 4+ years (design started 5+ years ago) still uses 72 pin EDO SIMMs. It&#39;s not that much trouble to get them and they are $5-$10 for 16-32MB stick. I agree that DDR would be an even better choice if you can develop the controller. The Twister Cyclone dev board on www.fpga.nl has DDR, but not in a socket. It may come with a controller that is close? I know I&#39;d like to have either one for a future board spin http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif Ken

Slightly OT, but I downloaded the Twister QII and SOPC files and built them. They have a very professionaly integrated DDR component that you can add to your design. It has choices for a couple of different Cyclone chips and a couple of different DDR chips. QII Timing analyzer says its good for close to 100MHz. They have the CPUCLK set at 66. Not sure what the licensing is but I&#39;ll bet you can use it if you purchase their devkit. Ken

From one of the engineers: We completely support SO-DIMM&#39;s, but do not at all support I2C -- our SDRAM controller only does static SO-DIMM configurations (set up in the wizard, pre-quartus compile). This should be reasonably well described in the SOPCBuilder SDR-SDRAM documentation. I&#39;m guessing that the user wants to have their system dynamically self-configure SDRAM at power-up, via I2C, to be able to talk to whatever (potentially new) SO-DIMM it happens to find. I believe that (aside from the fact that the controller can&#39;t do it) putting in a different SO-DIMM might change the address space requirements of the system, which the CPU and other system components can&#39;t deal with anyway. Since a rebuild would be required to change memory size/capacity anyway, you can reconfig your controller to match the new SO-DIMM at the same time. If this doesn&#39;t help, please reply. Heck, reply if it does help!

--- Quote Start --- originally posted by kerri+jul 14 2004, 11:56 am--><div class='quotetop'>quote (kerri @ jul 14 2004, 11:56 am)</div> --- quote start --- we completely support so-dimm&#39;s, but do not at all support i2c -- our sdram controller only does static so-dimm configurations (set up in the wizard, pre-quartus compile). this should be reasonably well described in the sopcbuilder sdr-sdram documentation.[/b] --- quote end --- yes, it was quite obvious in the documentation. i was just wondering if you guys were thinking of adding such a feature. <!--quotebegin-kerri@Jul 14 2004, 11:56 AM i&#39;m guessing that the user wants to have their system dynamically self-configure sdram at power-up, via i2c, to be able to talk to whatever (potentially new) so-dimm it happens to find. i believe that (aside from the fact that the controller can&#39;t do it) putting in a different so-dimm might change the address space requirements of the system, which the cpu and other system components can&#39;t deal with anyway. since a rebuild would be required to change memory size/capacity anyway, you can reconfig your controller to match the new so-dimm at the same time. --- Quote End --- The user just wants a lot of RAM. We could design around some SDRAM chips, but then we&#39;re at the mercy of some company keeping those chips in production. An SO-DIMM would be easier to deal with over the long haul, plus they&#39;re easier to route. Static worst-case timings are acceptable, as long as I can determine what such timings should be. Or I&#39;ll just spec some timings and see how well it does. I&#39;m running PC133 memory at PC66 speeds anyway, so it should be a bit more lenient. As for memory size detection, I figured we&#39;d just set up SOPC builder for the maximum and then detect how much is really there (if any) at boot time. Will this approach fail?

SDRAM Interface to SO-DIMM? | Altera Community

13 Replies

Altera_Forum
Honored Contributor
21 years ago
Mike,

Will your instruction source require all of this ram or could you get away with say a 16MB chip on board for code and use the SODIMM for data buffer?

That's kind of what we did with our last coldfire board. It has enough sram on board to run, but detects and uses whatever is in the EDO SIMM slot. So even if the stick goes bad the board still functions.

What mechanism if any (no MMU) in the Nios stops you from setting a pointer to any address you want and writing or reading? (as long as it exists)

May not apply to your case.

Ken
Altera_Forum
Honored Contributor
21 years ago
--- Quote Start ---
originally posted by kenland+jul 21 2004, 03:23 pm--><div class='quotetop'>quote (kenland @ jul 21 2004, 03:23 pm)</div>
--- quote start ---
will your instruction source require all of this ram or could you get away with say a 16mb chip on board for code and use the sodimm for data buffer?

that's kind of what we did with our last coldfire board. it has enough sram on board to run, but detects and uses whatever is in the edo simm slot. so even if the stick goes bad the board still functions.[/b]
--- quote end ---

we thought of that, but the goal for using an sodimm is to simplify things by having just one memory bank (hence, one memory bus). in our case, memory failure is pretty much system failure, so there's no benefit there, either. we may have the fatal exception vectors point to internal memory, where it will report the error to the outside world and then hit an infinite loop.

we're doing what you're talking about on a ti dsp board, which has internal and external ram banks. the code lives internally along with data/bss/stack/heap, and we have our own memory allocator that deals with the external memory for bulk use.

<!--quotebegin-kenland@Jul 21 2004, 03:23 PM
what mechanism if any (no mmu) in the nios stops you from setting a pointer to any address you want and writing or reading? (as long as it exists)
--- Quote End ---

You have to tell the SDRAM interface SOPC component what the maximum size is so it generates the proper addressing hardware and I/O pins. But if the software side assumes that you always have that much memory, there will be trouble. All I need is a mechanism to tell the software side to use only a minimum amount of the RAM, then I can manage the rest myself, but it would be easier if I could just tell the thing to move the top of the heap up and just use malloc/free. There may be a mechanism to do this; I haven't gotten that far yet.
Altera_Forum
Honored Contributor
21 years ago
Mike,

You're on the right track. You're right about the HW constraints (For the maximum size memory anyways). I believe what is necessary in your case is to diverge from the fully automatic SW dev flow and play with a linker script. If you make a SW project in the IDE, there will be a file called "generated.x", in the syslib project system description folder (I think). This file is what tells the linker where to put text, exception, bss, stack, heap, etc. Now I am no linker script expert and I hear fiddling with these can be 'fun' so to speak, so I'd recommend small incremental changes to meet your goals... however, it should be pretty straight forward: the sizes of memory (SDRAM for example) are defined here and they will control what the linker is allowed to use.

If you were to, for example, define a "minimum" SDRAM size that is linked against, and then# defined this into your application code, you might be able to do a walking memory test at boot up to figure out how big the SDRAM really is, and then use this information to know how much is available for your application to use.

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SDRAM Interface to SO-DIMM?

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