SDRAM and speed gain

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originally posted by alon2005@May 21 2006, 10:01 PM

as the sdram controlller does not offer a clock out for sdram,we need to generate the clock by pll and make connection to sdram clock input pin, my question is: how can the data synchronous wiht clock?can i make system clock for nios and sdram clock with different frequence?example sdram clock at 100m but nios system clock in is 50m...

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This has been discussed several times here.

You need 1 clock input that feeds the pll. the pll creates 2 clock output signals. let&#39;s assume c0 is the nios2 core clock and c2 the external sdram clock output. with the pll you have the possability to tune the sdram in order to get the sdram clock synchron with the fpga signals that feed your sdram (phaseshift) you should calculate the phase shift as mentioned by the altera AN??? very easy.

now you can have c0 and c2 running at a different clock speed as your clock input. lets assume clock input is 50MHz. you could have c0 with 75MHz and C2 with 100MHz with phase shift.

But be aware of that if you have different clock domains inside your fpga you will need clock domain crossing circuits. i doubt that running the core at a different clock speed (in your case 50MHz) as the sdram at 100MHz will lead to a faster system than having both of them running at 50MHz as the clock domain takes a couple of clocks to synchronise. i personaly tune the pll output in a way that both clock outputs (c0 for nios core and all sopc modules, also c2 for external sdram) have the same clock speed but the speed is faster than the external clock speed. in other words, external 50MHz internal >50MHz

regarding your question about synchronize the data .. that is handled by quartus. you just need to tune the pll phase shift as calculated.

It works perfect believe me :-)