SDRAM and speed gain

Yes. The purpose of a PLL is to take one clock signal (like the 50MHz signal on the development board) and produce another clock signal. With the produced output signal, you have the option of changing the frequency, phase, and jitter characteristics. So you instantiate a PLL in your firmware design. Provide the 50MHz clock as an input. Set the PLL to double the clock frequency to 100MHz. Then provide the 100MHz signal as the input to your SOPC system. So there is really no reason to change the crystal on your development board. The cyclone II on your board has 4 PLLs in it.

Then you can run your processor and SDRAM at the 100MHz clock without crossing clock domains. You can also provide more than one output clock from the PLL with different frequencies.

Now a second concern is timing. 100MHz is not very fast so you really shouldn't have problems running at this speed. Once you recompile the firmware project in Quartus the timing analyzer will tell you whether you are meeting timing requirements or not.

Hope this helps. If you have some more specific questions, let me know.