SDRAM and speed gain

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originally posted by kalle leo@Mar 16 2006, 06:52 AM

i want to build a system using sopc builder that contains a sdram controller, that is accessed from a nios2 and a dma controller, both running at 50mhz. if i have the sdram controller run at 100mhz, will this give me a speed gain, because memory access might be faster or will it slow things down because of logic needed for clock domain crossing?

on a completely unrelated note: has somebody used a quartz other than the 50mhz one the cyclone dev-kit ships with on one of these boards? what are your experiences?

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From experience I can guarantee that it will be slower due to the clock domain crossing. It takes several clock cycles for the clock synchronization modules to pass data. This has to occur both on the reads and the writes. You would be better off to avoid the clock synchronization modules.

I&#39;m not sure what FPGA you are using but typically you use a PLL to bump up the frequency. You don&#39;t really want to replace the crystal unless that is your only alternative. If you do, make sure you look at the board schematics for your development board and that your replacement crystal will work with the rest of the oscillation circuit (capacitors or resistors usually).