OK seems to be my hypothesis is supported by evidence. I changed the connection on the board (see my attached image "FPGAboard.jpg") and voila now it works. The pll1 out at pin 43 now connects with the sdram clk_in at pin38 of the SDRAM and the former connection to sdram_we now reconnects to pin 60 of the FPGA . I used this occasion also to exchange the blue led’s against green ones and I also increased the pre resistors up to 2k. Maybe one should consider to invest more money into a terasic evalboard – to my knowledge the DE series seems to be well engineered