I want sample the output of an ADC and store it in registers where it can be processed while another sample is taken. After reading through some Nios literature, it seems like the best way to do this is to use the Vectored Interrupt Controller and the Shadow register sets. Does anyone have an opinion about this? I'd like to write the values sampled from the ADC to the shadow registers. Thanks in advance

--- Quote Start --- I want sample the output of an ADC and store it in registers where it can be processed while another sample is taken. After reading through some Nios literature, it seems like the best way to do this is to use the Vectored Interrupt Controller and the Shadow register sets. Does anyone have an opinion about this? I'd like to write the values sampled from the ADC to the shadow registers. Thanks in advance --- Quote End --- It really depends on your ADC sampling rate, and what you want to do with the data. If your ADC operates under software control, eg., you enable it for a conversion and then get an interrupt when it is done, then a software solution would work fine. If however your ADC operates continuously at frequencies of ~MHz, then you will have to come up with a different scheme, eg., sampled data would be streamed to a data processing block, where some parameter was estimated by FPGA logic, eg., a power estimate. The NIOS processor would then access the results of the DSP processing at a much slower rate than the ADC clock rate. So what is your situation? Cheers, Dave

Thanks for your quick reply, the ADC is for an audio application so the output rate will be quite high. What I need to do first for my project is perform an offset correction and determine the frequency at the input(fast).

--- Quote Start --- The ADC is for an audio application so the output rate will be quite high. What I need to do first for my project is perform an offset correction and determine the frequency at the input(fast). --- Quote End --- In that case, you need to consider the signal processing separate from the NIOS processor. The processor can be used to configure the signal processing path, and to read results, but it would not be involved in processing of individual samples. What does 'offset correction' entail? Measuring the DC value of the signal, and then adjusting it until it is zero, or simply removing the DC component? Start by getting a simple example working first, eg., the DC offset, or perhaps the input power, and then work on the frequency estimation. You should also try and implement the software equivalent of the processing of the samples in a signal processing package like MATLAB. Its much simpler to develop algorithms and look at spectra in MATLAB, and then decide what needs to be implemented in hardware. Cheers, Dave

Yes, I am using MatLab to develop the algorithms, I've also been looking at the DSP builder link between MatLab and Quartus but not sure about that yet. The offset correction removes the DC offset, which I believe will make the data easier for the frequency estimation processing. Do I need to determine the input power for the processor? For the DSP block your referring to the Quartus megacores right?

--- Quote Start --- I am using MatLab to develop the algorithms --- Quote End --- Ok. --- Quote Start --- I've also been looking at the DSP builder link between MatLab and Quartus but not sure about that yet. --- Quote End --- I haven't used DSP builder. I prefer to code the VHDL directly. --- Quote Start --- The offset correction removes the DC offset, which I believe will make the data easier for the frequency estimation processing. --- Quote End --- That is probably correct; though it would depend on the algorithm you select. If you were to use an FFT, the DC component results in ringing across the frequency response. Its a good idea to remove it. The book "Understanding Digital Signal Processing", by Rick Lyons has example DC removal circuits. However, if your audio signal is AC coupled to your ADC, there should not be much of a DC offset. You should capture some data and investigate. --- Quote Start --- Do I need to determine the input power for the processor? --- Quote End --- No, but you will want to know if your signal is 'loud' enough, otherwise your ADC quantization noise will dominate. I was simply suggesting that you start by figuring out how to design a power measurement circuit, since it is very simple; hint its related to the average of a block of samples squared (simple to implement in hardware). --- Quote Start --- For the DSP block your referring to the Quartus megacores right? --- Quote End --- No, I just meant signal processing in general. You might want to use DSP blocks (the FPGA resource), but you can infer those by writing code like a*b, where a and b are appropriate sized std_logic_vectors; the Quartus handbook has coding style recommendations. Cheers, Dave

Sampling using the VIC | Altera Community

12 Replies

Altera_Forum
Honored Contributor
15 years ago
A further clarification on dc filter:

If the dc excess power is well away from your signal bandwidth then you can use less potent filtering.

If dc power is also part of your signal then you should use a very sharp filter with measured attenuation so that you only remove excess dc and pass your dc and the rest of power with minimum ripple.

The running average subtraction above is a feedback system and must lock in your application i.e. you need to apply correct loop filtering(basically your averaging order and the fraction of feedback) so that you avoid oscillation due to fast/slow subtraction or over/under subtraction.
Altera_Forum
Honored Contributor
15 years ago
Thank you both for the knowledge, I think I'm on the right direction now.
side note:
I had thought (was hoping) that because the nios processor is synthesized in the FPGA, it processes data like a circuit as the FPGA does. In any case, it doesn't matter it is a very flexible tool.

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Sampling using the VIC

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