Sampling using the VIC

Hi Sam,

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Can you tell me what relevant limitations the Nios processor has vs. the fpga, will it not process at the same speed the fpga does?

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A processor has to fetch instructions, fetch data, perform an operation, and then write the result somewhere. The FPGA fabric can process data in a 'streaming' fashion, where data comes in one set of ports, gets processed, and leaves by another set of ports. The only limit to the operating speed of that logic is the clock rate of the FPGA. If your ADC sampling rate exceeds the FPGA maximum clock rate, then you can still process the data, but you have to do it in parallel.

In many signal processing systems, processing is performed by the FPGA fabric, while a processor is used for control; enabling blocks, selecting processing blocks (multiplexer control), and monitoring what is going on. This is why the Avalon bus used by Altera has two implementations; the memory mapped Avalon-MM read/write interface for processor buses, and the streaming Avalon-ST unidirectional interface for connecting DSP blocks (or DMA, or whatever has a streaming nature).

Cheers,

Dave