Sampling using the VIC

Hi Dave,

I myself was a fan of coding by inference since it is compact and readable. This is certainly true for registers and most additions, shifts ...etc. but with multipliers I encountered some issues:

1) compilers tend to infer a mult per occurence in a construct and it does not realise when one mult can do the job. This can be easily avoided by coding style.

2) I can't decide pipeline inside inferred mults.

3) in stratix III/IV there is what is termed dsp element which is made up of 4 mults plus adders in a single block. This block has enough input ports for 4 mults but only 72 outputs meaning that you can only use 2 mults on their own(wasting two) or all 4 mults if you use adders inside. The compiler does not infer these blocks from code (unless there is special way). HDL inference coding needs to catch up for these mini-asic blocks inside fpgas.

With regard to DSPbuilder, I have started using it reluctantly. It offers wonderful development and iteration speed when it works but a painful dilemma if it does not, no one can repair the generated code. Interestingly, while it can be used by beginners , it can be used far more powerfully if designer has prior dsp knowledge. The resource usage and speed are impressive. But... its main drawback as any tool is on the skills of the workforce...