Forum Discussion
Altera_Forum
Honored Contributor
12 years agoYou need to think about how the code (etc) will get loaded into the memory areas.
If you plan loading from EPCS then only one nios can run the boot code. I'm not sure about JTAG, but having one copy is probably easier. We load code over PCIe - so can have completely separate nios systems, they are released from reset over the pcie. If you have 2 nios that are cooperating, it is probably easiest to compile and load the code as a single image - that way you don't have to worry about the actual addresses of items in shared memory. Use the gcc __attribute__((section("section_name")) and a custom linker script in order to get everything at the right physical addresses. The startup sequence is probably safer if one nios starts the other (eg after zeroing the bss and initialising other shared memory) even if you don't need the nios running in order to download the code. You'll need a short asm stub for the second nios to initialise the global registers (%sp, %gp and maybe the interrupt temporaries) before jumping to a C function. It is any of libc (eg printf) things are more difficult! For inter-nios communication use internal M9K memory blocks, tightly couple it to one nios and access from the other as an avalon slave (uncached). If you don't need access from anywhere else you can tightly couple to both nios. Make absolutely sure the shared memory is running from a single clock and has 'old data' selected for concurrent access (need qsys). For interlock use Dekker's algorythm,