Running programs on Nios II/e without JTAG UART

Hello everyone:

I'm trying to run some small programs on the Nios II/e processor core without the use of the JTAG UART component. I'm using the Nios II/e small example provided by the Nios II 5.0 Development kit. The program that I'm trying to run is the Nios II IDE's "Count_Binary" example.

--- note: the main reason i'm doing this is i'll be using another soft-core processor which does not contain a jtag uart core. (basically eliminates the use of the "nios2-download" shell command) in order to load and execute the program on the soft-core processor, it requires the generated/compiled of the c-program in a .hex file, compile the design with the .hex file and it will start executing once the entire design is loaded onto the fpga. this is my intended goal that i'm trying to achieve.

I felt that going through the Nios II/e "small example" might reflect exactly what I'll be doing with this other soft-core processor I'll be using.---

I'm going to describe the process in steps thoroughly so hopefully someone out there can tell me what I'm doing wrong or any missing steps I made:

1. I opened the Nios II/e small example from the Nios II Development Kit Version 5.0. I noticed that the "count_binary" example does not fit onto the on_chip memory as well the processor system is lacking in display features (e.g., LEDs, dual seven-segment displays).

2. I opened SOPC Builder and modified the contents of the Nios II/e processor system. I increased the "on_chip" ram to 64KB. I instantiated a timer ("sys_clk_timer"), 7 output PIOs ("led_pio"), and 16 output PIOs ("the_seven_seg_pio"). Also I have instantiated a UART core named "uart1". The block diagram of the Nios II processor slightly changed (as expected) and I assigned the appropriate PIOs and the UART rxd/txd pins of the Stratix Pro FPGA.

3. In Nios II IDE, I specified the "count_binary" project's program (instruction memory), read only memory, read/write memory, heap memory, everything all onto the 64KB "on_chip_64kbytes" memory. No other preprocessor settings were made.

4. I compiled the "count_binary" project using the "Build Project" option. In result, it generated a .hex file named "onchip_ram_64_kbytes.hex" and placed it in my Quartus II project directory.

5. Back to Quartus II, I compiled my entire design in Quartus II with the .hex file and downloaded onto the FPGA. Unfortunately the program did not start executing on the processor, which was the expected outcome.

6. I have tried doing a "nios2-run" command in the Nios II SDK SHell and unfortunately I was unable to download the program onto the processor system. Also, I did a "nios2-run -t" to observe any activity with the processor system and unfortunately nothing came up.

Technical Details:

- Altera Quartus II 5.0 SP2

- Nios II IDE 5.0

- Stratix Professional Edition FPGA Board (EP1S40 series)

The BDF of the small example specified these instructions (more or less). If anyone out there can please tell me where I have gone wrong in my process or give me some addition pointers that I can look into?

Thanks very much in advanced!