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Hi man,
Can you elaborate please, I'm having awful trouble. nios getting ext clock 50Mhz. SDRAM clock getting -3ns from a pll. Will not work.
This is simplified to a sentence, but that's basically it!
Cian
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I think you're inverting the clocks...
You must have to delay the nios clock by 3ns, and the SDRAM with no delay.
Your system will be like this:
PLL (external PLL, don't use SOPC or Qsys PLL I don'n know why but did not worked for me):
Create a PLL with 2 clock outputs, one for nios one for SDRAM, connect the 0ns delayed direct to the SDRAM input clock (physical pin) and connect the 3ns delayed clock to nios input clock wire, the nios output clock for SDRAM will be disconnected.:)
Honored Contributor
