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Hi, do you have flash in ur qsys system? If yes, I suppose you are gonna have 2 generic tristate controllers, tristate bridge and a tristate pin sharer connecting together. In your top level design, pls check its connection. For 16 bit sram, u should ignore the first bit and so on. I encourage you to have a look on qsys handbook, Tristate chapter. Hope it helps.
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PeFarina,
It is a common practice to share address and data pins between SRAM and Flash memory to reduce the number of pins required in your FPGA design. If this is your case, you need to add a pin-sharer module in SOPC Builder. I'm more familiar with Qsys, but I imagine the configuration is similar. I attached a screen shot of my Qsys design to show how the pin sharer connects the SRAM and Flash. If you have separate address and data pins for your SRAM, then you don't need the pin sharer.
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