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Altera_Forum
Honored Contributor
20 years agoRunning program in SDRAM
Dear all, I just solided on FPGA board with Cyclone and SDRAM. I tried the example Hello_World_Small program in on_chip_ram, and received the output via UART. Then I ...
Altera_Forum
Honored Contributor
20 years agoredsun,
> What may cause such problem? There are many potential causes. Here are some: - SDRAM was not placed correctly (shorts/opens on pads). - Bad traces between Cyclone and SDRAM. - SDRAM clock doesn't meet timing requirements. - Pins are not assigned correctly. - SDRAM timing parameters are incorrect. - SDRAM is not actually mapped to 0080_0000. Check the easy stuff first (pin assignment, timing parms, base addrs) first. The check your timing analyzer results against your board layout -- you may need to shift your SDRAM clock phase. Finally, break out a scope and add an SDRAM memory test to your hello_world that runs out of on chip ram Make sure you bypass/don't implement the data cache. Regards, --Scott