Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi, I assume you mean you want to expose the interface of the HPS GPIO controller to the FPGA fabric, and then connect an FPGA pin to be directly toggled by the GPIO. As far as I know, you can't do this for Arria 10 (this can be done in Cyclone V).
One way to overcome this is to generate an PIO IP in the FPGA, and connect that IP to the LWH2F bridge. The drivers (linux and baremetal) for this IP is readily available.