Forum Discussion
Altera_Forum
Honored Contributor
11 years agoOk many thanks ... the NIOS reset appears to be sourced via the JTAG debug module ...
I believe you indicate I need to control the NIOS reset explicitly , ie disonnect it from the JTAG debug reset and generate a reset to the system that starts once the FLGA is configured and receives the first functional clock. ? Thanks, Bob