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Altera_Forum
Honored Contributor
14 years agoYou need to assert the 'reset_n' signal for a significant period - I think it is sampled once per instruction.
The 'reset out' signal is driver for a single clock (or two?) each time the processor detects 'reset_n'. While 'reset_n' is asserted, the processer starts coming out of reset, reads the first instruction word, then resets itself again before executing it.