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Honored Contributor
Honored ContributorRESET THE NIOS PROCESS USING reset_n INPUT
Hello, i made a custom component in Qsys. This component has a reset input signal (conduit export) and a reset output signal (Reset Output interface). The reset output signal is connected t...
Altera_ForumHonored Contributor
Honored ContributorYou need to assert the 'reset_n' signal for a significant period - I think it is sampled once per instruction.
The 'reset out' signal is driver for a single clock (or two?) each time the processor detects 'reset_n'. While 'reset_n' is asserted, the processer starts coming out of reset, reads the first instruction word, then resets itself again before executing it.
