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Altera_Forum's avatar
Altera_Forum
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21 years ago

reset & configuration revisited

I have some custom boards (cyclone, NiosIIe 33Mhz) that exhibits strange behavior on reset (either full POR OR soft reset (DEV_CLRn)). The behavior is that the Nios sometimes executes the code at the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Adding the reset delay block solved it. Now the flash is well out of reset before the Nios does its first fetch. There is still some hash on the reset signal that looks like xtalk from the flash CS (less than optimal routing on the board). Before, that hash would strike when reset was still down at switching thresholds. Now it does not occur until reset is up at VCC - gotta like that. Still I think the erratic boot behavior had more to do with fetching (bad) instructions too early than with noise.