reset & configuration revisited

The PLL is a dedicated circuit in the FPGA so you do not have to worry about LE resources being used. The delay circuit in the reference designs are based off a 50 MHz clock (it's clocked off a crystal), and counts up. I looked at it and made my own reset block (easier to copy it between designs). It has 10 bits and when it rolls over it stops, so it counts for 1024 clock cycles off a 50Mhz clock that's 20ns * 1024 = 20 us (that's overkill so you may not need that much but if you don't care about startup delay that should work fine). I would give yourself at least 1us or the amount of time for the reset voltage to hit the right value (whatever is longest).

The reset block is a 10 bit counter with a little bit of logic so it's going to be around 12-15 LEs. So you are looking at a PLL and 15 LEs to help stabilize things. But if you don't already use a PLL in your circuit you don't need to add it (the delay was to implement a wait for the Nios core that was driven from the PLL, so in your case you just want to delay the core until the flash is ready).