Honored Contributor
Honored ContributorNo need for active probes - simply using a scope instead of the analyzer greatly reduces the loading (1M vs 100k).
Comparing the reset (DEV_CLRn) against the flash CS shows a problem. The Nios comes out of reset and starts fetching instructions from flash when DEV_CLRn gets to about 1.2v. The flash is not even ready at this point since its own reset is not considered high until about 2.3v. I have to assume the Nios is occasionally fetching junk during reset. Clearly it is not a good idea to use the same reset signal for both devices unless you can guarantee a very fast edge. The Nios core reset would probably need to be delayed in most designs using flash. I have few resources (LEs or pins) to implement an internal solution but that is still preferrable to adding components. Does enabling the PLL really use any LEs, and is there a mininum delay associated with waiting for lock? thanks
