Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

reset & configuration revisited

I have some custom boards (cyclone, NiosIIe 33Mhz) that exhibits strange behavior on reset (either full POR OR soft reset (DEV_CLRn)). The behavior is that the Nios sometimes executes the code at the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

My reset is provided by a LT power supervisor that monitors 5,3.3,1.5. I have probed the sensing pins and there are no glitches. It would have to be very noticable since the chip filters out power glitches. The noise on reset has to be xtalk from adjacent traces or from one of the half dozen devices it drives. My rise time is 4x slower than the 40ns specified, but it is not the source of noise. CONF_DONE and nSTATUS are pulled up as indicated in the cyclone datasheet for one EPCS device.

Hmm.. I just noticed an odd thing. I was probing the reset signal and the flash CS on the same pod of a logic analyzer. When I remove the probe from the flash, the reset cleans up. There is some loading from the probe - I'll have to investigate further.