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Altera_Forum
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21 years ago

reset & configuration revisited

I have some custom boards (cyclone, NiosIIe 33Mhz) that exhibits strange behavior on reset (either full POR OR soft reset (DEV_CLRn)). The behavior is that the Nios sometimes executes the code at the...
Altera_Forum's avatar
Altera_Forum
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21 years ago

What does your reset circuit look like?

Also the CONFIG_DONE, nSTATUS pins are pulled high in some designs. I would read up on those pins to learn more though.

The posts about the delay on reset are talking about delaying the reset signal so that you can be assured the clock coming out of the PLL are stable (if you don't use PLLs then you may not need this circuit, but it would be handy to help debounce a reset switch if that's present). To see this circuit look at a reference design in your Nios II installation folder.