Required Timing Assignments for SDRAMs

Hello,

Currently I’m working with a custom board which is equipped with a Cyclone EP1C12Q240C7 and two 128Mb SDRAMs from Micron (16bit, 48LC8M16A2-75). There’s also some other stuff on the board but I think that’s not important for this topic. All SDRAM signals are connected directly to the SDRAM without any other devices so the SDRAM has its very own bus. The clock is connected to an output of one PLL which is driven by a feedback clock of the other PLL (like it is made on the development boards from Altera).

Until now the system was running with 50 MHz. Now I would like to give some more speed, for example 80 – 100 MHz. I tested the behavior when changing the PLL up to 100MHz with a simple Nios II processor (30% of available LCs). All was working well with 100MHz!

After that I tried to change the PLL with the normal implementation (60% of available LCs). This fails. The maximum frequency which is possible is 60MHz.

I think it is necessary to define some timing assignments for the SDRAM signals. But I really don’t know how. Could someone explain which settings are required?

Thank you in advance,

niosIIuser