Required Nios components

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DDR2 pins are OK, I have taken them from a working example from development board CD.

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Do you mean you tested the example on the same board? Or is this your custom board which pin locations have been copied from the dev board?

I don't think the problem is with ddr, since debugging tools should be able to get the correct sysid even if memory is not working. IMHO it's more probable the Nios is not working.

Maybe a problem with input clock or reset signal. Are you sure the fpga has been correctly configured?

Anyway I'd suggest this simple method to exclude ddr: you can temporarily replace it with onchip memory; this is enough for a "Hello world" kiind of program and it will let you take away any concern regarding external connections.

I have replaced the DDR2 memory with on-chip memory (262144 bytes), but the issue somehow was 125MHz clock. I have set the 50MHz clock instead and the Nios started.

The 125MHz clock was running for sure, I have made a blinker which works either with 125MHz clock or with 50MHz clock.

The development board is Cyclone III Host board from Altera (2 clocks on board + SMA IN)

Now the strange problem is that the console doesn't show anything. It runs the CPU:

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Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Processor is already paused

Reading System ID at address 0x00081030: verified

Initializing CPU cache (if present)

OK

Downloading 00040000 ( 0%)

Downloading 00045CD0 (71%)

Downloaded 24KB in 0.4s (60.0KB/s)

Verifying 00040000 ( 0%)

Verifying 00045CD0 (71%)

Verified OK

Starting processor at address 0x00040184

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I've checked BSP parameters, the stdin/stdout/stderr are all set to uart_jtag, but the console screen is empty.

Can you toggle a PIO from your Nios program? This way you may know if processor is running, independently from jtag uart operation.

But first of all, is your design correctly time constrained? Did you get any critical warning during Quartus compilation? You must be careful with Nios designs using f>100MHz on CIII because timing problems can easily occur.

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Can you toggle a PIO from your Nios program? This way you may know if processor is running, independently from jtag uart operation.

But first of all, is your design correctly time constrained? Did you get any critical warning during Quartus compilation? You must be careful with Nios designs using f>100MHz on CIII because timing problems can easily occur.

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I will try to do that, but I've also tried to run debug. The output says, that the processor is started, but when the debug window comes up, I see the processor "terminated". I don't know why is this happening.

There are 4 critical warnings because of constraints, but those are common and not familiar with Nios. Something like clock uncertainty on JTAG TCK pin, actually can't remember now the exact warning...

In addition, Nios now runs on 50MHz directly from the clock, so should be fine.

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you can choose to ignore mismatched timestamp and sysid under run as -> run-configurations -> target connection

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Yes, I know, but this is used for mismatched systems, that are familiar. E.g. You use somewhere compiled .sof file, but generate Your own Nios code. This feature doesn't work, when the core is not running. ID and timestamp fields are marked "Not found".

Thanks for the help.

hi guys .........

socrates if your cpu run at 50Mhz and your ram run at 125Mhz you need to put a clock crossing bridge......

your problem seens to me a interface with your ram......

try put in you sopc

cpu -> clk 62.5 (altmenddr.halfrate)

jtag

pio

clock crossing bridge 62.5 -> 125

ram -> 125

this work fine

good luck

Franz Wagner

ok...... now i see.....

hum.....i have a cyclone iii dev board too....

i do a simple system to test and it works

starts with 50mhz all components and rise clock by steps

try do that

cheers

Franz Wagner

Are you sure the compiled design meet all timing requirements? In my experience it is difficult to make the NIOS CPU run over 100MHz without a pipeline bridge before the JTAG debug module.

I agree with frantz... Try to run your system at 50MHz first, and then increase the speed from there.

Probably You're right. I have set the ddr controller to run at half rate (125MHz/2=62.5MHz), doubled the burst and now Nios runs fine, no need of pipeline bridge.

Thanks for help... Time to test SGDMA! Or maybe modular sgdma is better? Still confused, I need to transfer coded video data in packets to Nios, add IP header and proceed to TSE :)