Forum Discussion
Altera_Forum
Honored Contributor
21 years agoif you have data cache in your system then in order to access a peripheral you must either set the 31st address bit high or use the IORD and IOWR macros (which set the 31st bit high). When the 31st bit is high the Nios will bypass the data cache and directly access the peripheral (periphals you do not want to be cacheable). So with this 31st bit determining the caching, you effectively have 2GB of address space (cacheable and non-cacheable).
If you don't perform cache bypassing with something like a hardware peripheral that you always read from you will get the following behaviour First read will access the peripheral and read data from it Second read will not access the peripheral and the read data will be the same as in the first step (since the data is cached). Hope that helps.