read and write timings on avalon interface

Thank you for your answers!

I've done some digging and the the 14 clock cycles appear to be caused by the clock domain crossing logic...

My code is run from internal M9K memory.

Just to be clear, I measured the 14 cycles this way:

write 1 to pio

write value to peripheral

write 0 to pio

write 1 to pio

write 0 to pio

write 1 to pio

write same value to peripheral

write 0 to pio

This way all the required values were stored in registers and the only operations made were writes (checked objdump). Writing to pio needed 2 cycles, and writing to peripheral then pio required 16 cycles...

Next week I want to try to run the avalon interface logic at 100MHz so it will have no delays and the rest of my peripheral on a clock divided by 2.