Forum Discussion
Altera_Forum
Honored Contributor
20 years ago1.
Yeah, It is. 2. You can specify the Timing of USB in the "avalon slave timing" of "interface" Tab. The time/ cycle you added will implement by your "system clock" in FPGA logic. 3. I think it is the best/only choice, cause it is a "register" device. ( there are regesters in the device) While the memory device, such as SRAM, flash should using "memeory(Dynamic addressing)" interface. 4. " page 6-26 from Quartus II Handbook, Volume 4" talks about "The Avalon tristate address" not the avalon slave. Avalon slave will connects slave's A0 to Nios(master)'s A2..A0 depending on the data-width of your slave. SO what you test is right/normal/successful way. Do you using "Add HDL files..." to start make your own comoponets? It is also meas: do you write a hdl to add the components?