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otto-Q's avatar
otto-Q
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1 month ago

Nios V/g load-writeback hazard

Summary On a NiosV/g core, a long-latency load from an on-chip memory immediately followed by a short-latency load from the core's own TCM returns the TCM load's data in both destination registers. ...
Nios Cpu
otto-Q's avatar
otto-Q
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1 month ago

Thanks for the answers! I/we will test with Quartus 26.1 and report back to you after that

tehjingy_Altera's avatar
tehjingy_Altera
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1 month ago

Hi otto-Q 

Did you managed to try out on the Quartus 26.1? 
Are you still facing the same issue?

 

 

  • otto-Q's avatar
    otto-Q
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    1 month ago

    Sorry, not yet, this is delayed by some days due to internal reasons