Occasional Contributor
Occasional ContributorThis is expected behavior in newer Quartus versions. The Nios II processor does not auto-insert the JTAG UART or the JTAG-to-Avalon bridge. You need to:
Manually add the JTAG UART IP (for terminal I/O) or JTAG to Avalon Master Bridge (if needed for memory access during debug).
You do not export JTAG pins manually in Platform Designer — these are handled outside of Platform Designer in the top-level Quartus project.
So for clarification:
jtag_uart_0 is not a physical JTAG interface — it's a virtual UART over the JTAG debug cable, so it doesn't need export.
The real JTAG pins (TDI, TDO, TMS, TCK) are already handled by Quartus I/O assignments (you don’t add them in Platform Designer).
You only export other peripheral interfaces (e.g., clk, reset, external memory), not JTAG pins.
To get NIOS II + JTAG UART working:
Add Nios II processor in Platform Designer.
Add JTAG UART IP manually.
Connect:
clk to system clock.
reset to system reset.
irq to Nios II's interrupt line (optional but recommended).
You do not need to export jtag_uart_0 — Quartus uses it automatically via USB Blaster.
After generating HDL, compile the project.
In Nios II SBT, you should see JTAG UART available for terminal connection.
I recommend referring to the following official Intel resources, which provide clear guidance on working with Platform Designer and Nios II systems. These documents should help clarify many of your questions and allow you to explore the design flow in more detail.
Please go through these resources as they cover the fundamentals and should address most of the questions you've raised.
