Configure NIOS firmware burning interface

Hi,

1) JTAG Programming

In Platform Designer (formerly Qsys), if you're using a NIOS II system, you typically do not need to manually add a JTAG interface block. Instead:

• The JTAG interface comes automatically when you add a NIOS II processor, and it is used via the JTAG UART or JTAG Debug Module (DM).

• If you're looking for physical JTAG pin connections (TCK, TMS, TDI, TDO), those are part of the FPGA hardware design, not something inserted via Platform Designer. You handle them in the top-level Verilog/VHDL design or via the Pin Planner in Quartus.

To check or export JTAG pins:

• Open the Quartus project’s top-level design file (e.g., top.v or top.qsf).

• Use Assignment Editor or Pin Planner to assign JTAG signals to the correct FPGA pins (these are often automatically assigned depending on your dev board).

2) IRQ Column:

In Platform Designer:

• The IRQ column (Interrupt Request) defines the interrupt priority or vector number when you connect a peripheral (like a timer or UART) to the NIOS II processor.

• The number you enter (e.g., 1, 2, 3, etc.) determines the interrupt number that peripheral will use.

Rules:

• Each IRQ number must be unique for each peripheral.

• Lower numbers can be treated as higher priority depending on your interrupt controller setup.

Do you need to change them?

• Yes, if you have multiple interrupt-generating components, assign each a unique IRQ number.

• If your system only has one interrupt source, then you may just use 0 or any number as needed.