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Altera_Forum
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19 years ago

rasied cosine implementation using FPGA

good evening!

Im a 4th year student in college for BS.c in electronics and engineering. im currently working on my final project which is called Simulation and realization of Raised Cosine filter for I.S.I. cancellation.

I was wondering if theres anyone on here who knows how can i program the FPGA i was given in order to create such a Raised Cosine filter?

im working with Quartus II for NIOS 2 development board, model: EP1S10780C6

if anyone can help me get started or can contribute in anyway i would very much appreciate it ! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/tongue.gif

thx and good day.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    --- Quote Start ---

    originally posted by popcorn@Nov 10 2006, 04:41 AM

    good evening!

    im a 4th year student in college for bs.c in electronics and engineering. im currently working on my final project which is called simulation and realization of raised cosine filter for i.s.i. cancellation.

    i was wondering if theres anyone on here who knows how can i program the fpga i was given in order to create such a raised cosine filter?

    im working with quartus ii for nios 2 development board, model: ep1s10780c6

    if anyone can help me get started or can contribute in anyway i would very much appreciate it ! http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/tongue.gif

    thx and good day.

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=19358)

    --- quote end ---

    --- Quote End ---

    Sure. I&#39;ve implemented one on my current project. email me privately with your questions. katanabill at yahoo dot com.