RAM and FLASH shared bus don't worked

Hi mmTsuchi,

Thanks for your reply,

I'm working on the project with Judau and config for this project.

About hardware:

+ I'm using the sdram 8Mbyte of Micron and using sdram controller core and check in (Share pins via tristate bridge, Tristate bridge selection i had chossed the tri_state_bridge which handle the cfi_flash). About timing of sdram controller i setting default.

+ I'm using the cfi_flash S29AL032D of Spainsion and using the CFI controller core. Address width is 21, Data width is 16 because cfi_flash sharing data and address with sdram (limited i/o pin in hardware). About the timing 40-160-40ns. And in the schematic WP#, RY/BY# pull up 4k7 resitor to 3V3, and pin 47 BYTE# (F_MODE) control by FPGA (assign F_MODE = 1'b1

And i had made on chip ram 24KB for testing.

The reset_vector using cfi_flash.

The exception_vector using sdram.

The nios ii config .text, .rodata, .rwdata, heap and stack i setting at sdram.

My problem now is when i set .text, .rodata, .rwdata, heap and stack i setting at on chip ram and programing to cfi_flash complete after reset the LED test blink ok but when i set .text, .rodata, .rwdata, heap and stack i setting at sdram, the nios not working.

Can you help me!

Thanks and Regard!.

Q.Cuong.