Question about Nios2 Min system.

Sorry about that, I didn't notice which core you are using.

In case you move up to the 'f' core here's my second shot:

In Nios I (the first one from years back), when you had data cache available in the system in order for your data to bypass the cache all you did was declare your register pointers to be volatile. The keyword volatile tells the compiler to not synthesize out the variable if it believes it can along with bypassing the cache (like if you keep reading from an external register the compiler will think that's pretty dumb and optimize all the other reads because you already should have the data). Bypassing the cache prevents a similar problem where you perform one access to that register, it become stored in the cache then each time you go to read from it again, if it is still in cache then it will read the value from cache and not the register (so it'll look like the register never changes value).

In Nios II volatile is now in the pure form, meaning that it will not sythesize the variable away but it no longer bypasses the cache for you. It's still a good idea to declare your pointers with volatile to make sure they don't disappear after the compile, but you now have to use IORD and IOWR which are macros that set bit 31 for you (hardware sees that bit high and knows to read from memory and not cache).

Hope that clarifies what I tried to say before.