Question about 32 bits master

Hi!

I have designed avalon master-slave module for working with data from 16 bits SDRAM and 32 bits SDRAM.

This module consists from slave (for module control) and master (reading data from SDRAM).

When I'm trying to read the data from 16 bits SDRAM there always return 32 bit data (addr+0 and addr+2),

but I need the data only from addr+0 or only addr+2. How I can to do it? I'm using NIOS2.01. CPU is 32 bits.

For example 16 bits SDRAM mapping:

.....

0x00800000 aaaa

0x00800002 bbbb

0x00800004 aaaa

0x00800006 bbbb

.....

I need read address 0x00800002 and get only bbbb.

For reading 16 bits from SDRAM (bandwidth-16) I'm setting next signals:

...

byteenable <= 4&#39;b0011;

read <= 1&#39;b1;

address <= 0x00800002;

...

if (!waitrequest) begin

data <= readdata[15:0];

read <=1&#39;b0;

end

...

Is it right?

This my module ports:

input clk;

input reset;

//Master ports

output [31:0] address;

output [3:0] byteenable;

output read;

input [31:0] readdata;

output write;

output [31:0] writedata;

input waitrequest;

//Slave ports

input chipselect;

input [1:0] saddress;

input swrite;

input [31:0] swritedata;

output irq;

Thank you for any help.