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Altera_Forum
Honored Contributor
Honored ContributorQuery FPGA device ID from Linux
We have a board that accepts both an Cyclone V SX or ST part, and also one with more or less logic. Given device availability varies considerably, we have some boards built with one part and some wi...
Altera_ForumHonored Contributor
Honored ContributorI think you're looking for the Scan Manager ?
--- Quote Start --- The scan manager is used to configure and manage the HPS I/O pins, and communicate with the FPGA JTAG test access port (TAP) controller. The scan manager drives the HPS I/O scan chains to configure the I/O bank properties before the pins are used by the peripherals in HPS. The scan manager can also optionally communicate with the FPGA JTAG TAP controller to send commands for purposes such as managing cyclic redundancy check (CRC) errors detected by the FPGA control block. When the scan manager communicates with the FPGA JTAG TAP controller, input on the FPGA JTAG pins is ignored. --- Quote End ---
