Altera_Forum
Honored Contributor
20 years agoQuartusII Analysis&Synthesis question
I have build a NiosII hardware system. I have make sure it works well on my board. Today I reopened it in SOPC Builder, added an extra PIO component, regenerated the niosII cpu , update it in my .bdf file. However, a strange error existed during the Analysis&Synthesis prosess.
Error: Can't open encrypted VHDL or Verilog HDL file "D:/dev1/cpu_0.v" -- current license file does not contain a valid license for encrypted file Error: Node instance "the_cpu_0" instantiates undefined entity "cpu_0" Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 190 warnings Error: Processing ended: Thu May 11 11:54:22 2006 Error: Elapsed time: 00:00:05 I have never seen these errors before. My design has been working well on my board all the time. Why such problem takes place when I re-edited and update the design? Please help me! Thanks for all.