Qsys to custom HW interface

I am trying to connect Qsys to on-chip logic outside the Qsys environment and would like for the logic to appear to the Nios II SW as a wrtie-able location (such as RAM). In other words, when SW writes to this address it generates an external write signal along with the output data. I also need to read from a separate address.

I use this method to connect to external SRAM with no problem, but it does not seem to work with on-chip logic.

The problem with a PIO is that it does not generate a write signal. I suppose I could create one as on of the PIO bits, but that's a lot of extra SW that I would rather do without.