Qsys suddenly fails to generate HDL for my working code.

Altera 14.1

NiosII Qsys system

Cyclone CVGT board

Windows 10

This has been working for years up until this week. Now QSYS is failing to build the HDL for my design.

I'm guessing a Windows 10 update broke something. This was all working fine literally last week.

We have paid licenses for Quartus 14.1, and for DSP Builder and they have been working fine for us so no, I don't want to update the tools and pay for new stuff.

Yes, I am working on setting up Linux on a different PC to work around this issue.

In the meantime,

Here are the errors from Qsys:

Error: s0: Error during execution of "{C:/altera/14.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: s0: Execution of command "{C:/altera/14.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: s0: Authorized application C:\altera\14.1\quartus\bin64\jtagserver.exe is enabled in the firewall.
Error: s0: ]2;Altera Nios II EDS 14.1 [gcc4]C:/altera/14.1/quartus/bin64/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../qsys_core_uniphy_ddr3_s0_AC_ROM.hex -inst_rom ../qsys_core_uniphy_ddr3_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000100001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100100000 -DAC_ROM_MR1=0000000000110 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001000001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011000000 -DAC_ROM_MR1_MIRR=0000000000110 -DAC_ROM_MR2_MIRR=0000000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0
Error: s0: UniPHY Sequencer Microcode Compiler
Error: s0: Copyright (C) 1991-2010 Altera Corporation
Error: s0: Info: Reading sequencer_mc/ac_rom.s ...
Error: s0: Info: Reading sequencer_mc/inst_rom.s ...
Error: s0: Info: Writing ../qsys_core_uniphy_ddr3_s0_AC_ROM.hex ...
Error: s0: Info: Writing ../qsys_core_uniphy_ddr3_s0_inst_ROM.hex ...
Error: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: s0: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: s0: Info: Writing ../sequencer_auto_h.sv ...
Error: s0: Info: Microcode compilation successful
Error: s0: C:/altera/14.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: s0: child process exited abnormally
Error: s0: Cannot find sequencer/sequencer.elf
Error: s0: An error occurred
while executing
"error "An error occurred""
(procedure "_error" line
invoked from within
"_error "Cannot find $seq_file""
("if" then script line 2)
invoked from within
"if {[file exists $seq_file] == 0} {
_error "Cannot find $seq_file"
}"
(procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
invoked from within
"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
("if" then script line 2)
invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
(procedure "generate_qsys_sequencer_sw" line 877)
invoked from within
"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."
invoked from within
"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."
("if" else script line 2)
invoked from within
"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
(procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 212)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
invoked from within
"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
(procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"
invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {
set file_name [file tail $genera..."
(procedure "generate_synth" line
invoked from within
"generate_synth qsys_core_uniphy_ddr3_s0"
Info: s0: "uniphy_ddr3" instantiated altera_mem_if_ddr3_qseq "s0"
Error: Generation stopped, 1069 or more modules remaining
Info: qsys_core: Done "qsys_core" with 286 modules, 237 files
Error: ip-generate failed with exit code 1: 21 Errors, 19 Warnings
Info: Finished: Create HDL design files for synthesis